1. Field of the Invention
The present invention relates to a semiconductor device having a capacitor and a method of manufacturing the same, and more specifically, it relates to a semiconductor device having a capacitor of a roughened surface shape and a method of manufacturing the same.
2. Description of the Prior Art
In recent years, the demand for semiconductor devices is rapidly expanded due to remarkable popularization of information devices such as computers. In function, a semiconductor device having a large storage capacity and capable of performing high-speed operations is required. Following this, technical development is progressed in relation to improvement in degree of integration and high-speed response or high reliability of the semiconductor device.
A DRAM (dynamic random access memory) is generally known as a semiconductor device capable of inputting/outputting stored information at random. This DRAM is formed by a memory cell array serving as a storage area storing a number of information and a peripheral circuit controlling memory cells included in the memory cell array for inputting/outputting the information from/to an external device.
The memory cell array occupies a large area on the semiconductor chip of such a DRAM. A plurality of memory cells for storing unit information are arranged on the memory cell array in the form of a matrix. Each memory cell is generally formed by a single MOS (metal oxide semiconductor) transistor and a single capacitor connected thereto, and widely known as a one transistor-one capacitor memory cell.
FIG. 23 is a schematic sectional view showing the structure of memory cells of a DRAM employed as a conventional semiconductor device having capacitors. Referring to FIG. 23, a plurality of MOS transistors 120 are formed on a surface of a silicon substrate 111 electrically isolated by a trench isolation 123.
Each MOS transistor 120 includes a pair of source/drain regions 112 having an LDD (lightly doped drain) structure, a gate oxide film 113 and a gate electrode layer 114. The gate electrode layer 114 has a polycrystalline silicon layer (hereinafter referred to as a doped polysilicon layer) 114a doped with an impurity and a tungsten silicide (WSi2) layer 114b. 
A silicon nitride film 115 is formed on the gate electrode layer 114, and a silicon oxide film 116 is formed to cover the periphery thereof. A pad layer 117a and a bit line 117b are connected to the first and second ones of the pair of source/drain regions 112 respectively. An interlayer isolation layer 118 is formed on the overall surface of the silicon substrate 111 to cover the pad layer 117a, the bit line 117b and the MOS transistor 120. A plug layer 119 is embedded in a hole 118a of the interlayer isolation layer 118 to come into contact with the pad layer 117a. A silicon nitride film 124 and a BPTEOS (borophosphotetraethyl orthosilicate) film 104 are formed on the interlayer isolation layer 118. An opening 106 for each storage node 101 is formed in the silicon nitride film 124 and the BPTEOS film 104.
Each capacitor 110 has the storage node 101, a capacitor dielectric layer 102 and a cell plate 103. The storage node 101 is formed along the side wall and the bottom wall of the opening 106, and electrically connected to the source/drain regions 112 through the plug layer 119 and the pad layer 117a. The cell plate 103 is formed to be opposed to the storage node 101 through the capacitor dielectric layer 102.
A method of manufacturing the conventional semiconductor device having capacitors is now described.
FIGS. 24 to 28 are schematic sectional views showing the method of manufacturing the conventional semiconductor device having capacitors in the step order. Referring to FIG. 24, the MOS transistor 120, the pad layer 117a, the bit line 117b and the like are formed on the surface of the silicon substrate 111 formed with the trench isolation 123. Thereafter the interlayer isolation layer 118 is formed to cover the surfaces thereof, and the plug layer 119 is formed to be electrically connected with the pad layer 117a. The silicon nitride film 124 and the BPTEOS film 104 are formed on the overall surface of the interlayer isolation layer 118.
Referring to FIG. 25, the opening 106 for the storage node 101 is formed in the silicon nitride film 124 and the BPTEOS film 104 by general photolithography and etching.
Referring to FIG. 26, an amorphous silicon layer (hereinafter referred to as a doped amorphous silicon layer) 101 doped with an impurity is formed on the overall surface and thereafter subjected to surface roughening. Thus, the doped polysilicon layer 101 is formed with a roughened surface.
Referring to FIG. 27, photoresist 131 is embedded in the opening 106. Anisotropic etching (etchback) is performed on the overall surface through the photoresist 131 defining a mask, until at least the upper surface of the BPTEOS 104 is exposed. Thereafter the photoresist 131 is removed.
Referring to FIG. 28, the doped polysilicon layer 101 is left along the side wall and the bottom wall of the opening 106 through the aforementioned etchback, to form the storage node 101. Thereafter a natural oxide film is removed through buffer hydrofluoric acid (BHF) employing a mixed solution of hydrofluoric acid and ammonium fluoride.
Then, the capacitor dielectric layer 102 and the cell plate 103 are formed for manufacturing the semiconductor device having the capacitors 110 shown in FIG. 23.
However, the conventional semiconductor device having capacitors is inferior in reliability. This problem is now described in detail.
(1) In the storage node 101 subjected to surface roughening as described above, crystal grains 101b of silicon grow on an underlayer 101a consisting of doped polysilicon, as shown in FIG. 29. In this state, etching is performed with BHF in the conventional method for removing the natural oxide film. However, this BHF contains the mixed solution of hydrofluoric acid and ammonium fluoride, and this ammonium fluoride etches silicon.
Therefore, it is apprehended that the crystal grains 101b readily separate from the underlayer 101a in FIG. 29 and the separating crystal grains 101b adhere to the upper surface of the BPTEOS film 104 as shown in FIG. 30. In this case, the storage node 101 may be shorted to the adjacent storage node 101 by the re-adhering crystal grains 101b, to reduce the reliability of the semiconductor device.
(2) In general, the etchback step shown in FIGS. 27 and 28 is carried out through anisotropic etching. In this anisotropic etching, a residue is left along the side wall of the pattern due to the anisotropy of the etching. After the etchback step, therefore, the upper end of the storage node 101 defines a sharp forward end 101c along the side wall, as shown in FIG. 31.
When etching is thereafter performed with BHF for removing the natural oxide film, the upper surface of the BPTEOS film 104 is removed and the forward end 101c projects beyond the upper end of the BPTEOS film 104, as shown in FIGS. 32 and 33. The projecting forward end 101c is readily broken and separated due to vibration in a later washing step or the like. The separated forward end 101c may adhere to the upper surface of the BPTEOS film 104. In this case, the storage node 101 is shorted to the adjacent storage node 101 to reduce the reliability of the semiconductor device, similarly to the aforementioned case (1).
(3) Aqueous hydrofluoric acid (HF+H2O) may be employed in place of BHF, in order to remove the natural oxide film. In this case, however, P (phosphorus) contained in the storage node 101 for providing conductivity is eluted from the surface of the storage node 101 into the aqueous hydrofluoric acid as phosphoric acid (PO3), as shown in FIG. 34. Thus, the storage node 101 is reduced in conductivity, to reduce the capacitance as well as the reliability of the semiconductor device.
(4) When the spaces between the crystal grains 101b on the surface of the storage node 101 are narrow as shown in FIG. 35, the cell plate 103 cannot sufficiently fill up the clearances between the crystal grains 101b. Therefore, the opposed areas of the storage node 101 and the cell plate 103 are reduced to reduce the capacitance as well as the reliability of the semiconductor device.
An object of the present invention is to provide a semiconductor device having high reliability and a method of manufacturing the same.
A semiconductor device having a capacitor according to an aspect of the present invention includes a semiconductor substrate, a silicon nitride film, a first silicon oxide film, a second silicon oxide film and a lower electrode of a capacitor. The semiconductor substrate has a conductive region at the main surface. The silicon nitride film is formed on the main surface of the semiconductor substrate. The first silicon oxide film is formed on the silicon nitride film, and contains an impurity. The second silicon oxide film is formed on the first silicon oxide film, to substantially contain no impurities. An opening is formed through the silicon nitride film and the first and second silicon oxide films. The lower electrode of the capacitor is electrically connected with the conductive region and formed along the side wall and the bottom wall of the opening.
In the semiconductor device having a capacitor according to this aspect of the present invention, the second silicon oxide film formed on the first silicon oxide film substantially contains no impurities such as phosphorus and boron, dissimilarly to the first silicon oxide film. Therefore, the second silicon oxide is more hardly etched by aqueous hydrofluoric acid than the first silicon oxide film, and serves as an etching stopper. Thus, aqueous hydrofluoric acid can be employed for removing a natural oxide film from the surface of the lower electrode. In such etching with hydrofluoric acid, silicon is harder to etch as compared with etching with buffer hydrofluoric acid containing ammonium fluoride. Therefore, silicon crystal grains of the lower electrode can be prevented from separating from an underlayer of silicon and the lower electrode can be prevented from being shorted to another lower electrode, whereby the semiconductor device is improved in reliability.
Preferably in the aforementioned aspect, the upper end of the lower electrode is located downward beyond the upper surface of the second silicon oxide film.
Thus, the lower electrode is prevented from being shorted to another lower electrode resulting from breakage of the upper end of the lower electrode projecting beyond the upper surface of the second silicon oxide film, and the semiconductor device is improved in reliability.
Preferably in the aforementioned aspect, the lower electrode consists of a material containing silicon. An impurity supplying conductivity is introduced into the lower electrode in impurity concentration of the solubility limit of silicon.
Thus, the lower electrode has high conductivity, whereby a large capacitance can be ensured and the semiconductor device is further improved in reliability.
Preferably in the aforementioned aspect, the first silicon oxide film is prepared from an organic raw material to contain phosphorus and boron, and the second silicon oxide film is prepared from an organic raw material to substantially contain no impurities.
Thus, the second silicon oxide film can be more hardly etched by aqueous hydrofluoric acid than the first silicon oxide film.
A semiconductor device having a capacitor according to another aspect of the present invention includes a semiconductor substrate, an insulating layer, a lower electrode of a capacitor and a capacitor dielectric layer. The semiconductor substrate has a conductive region at the main surface. The insulating layer is formed on the main surface of the semiconductor substrate, and has an opening. The lower electrode of the capacitor is electrically connected with the conductive region, and has a surface formed of a plurality of crystal grains arranged along the side wall and the bottom wall of the opening at a space from each other on the surface thereof. The capacitor dielectric layer covers the lower electrode, and has a thickness less than half the space between the crystal grains of the surface of the lower electrode.
In the semiconductor device having a capacitor according to this aspect of the present invention, the capacitor dielectric layer, having the thickness less than half the space between the crystal grains on the surface of the lower electrode, is not completely embedded in clearances between the crystal grains. Therefore, an upper electrode can fill up the clearances between the crystal grains of the lower electrode to increase opposed areas of the lower electrode and the upper electrode, whereby a large capacitance can be ensured and the semiconductor device is improved in reliability.
Preferably in the aforementioned aspect, the semiconductor device further includes an upper electrode of the capacitor formed between the lower electrode and the side wall of the opening to be opposed to the lower electrode with the capacitor dielectric layer therebetween.
Thus, the lower electrode can be opposed to the upper electrode on both of the surface closer to the insulating layer and the opposite surface, whereby the capacitance can be increased and the semiconductor device is further improved in reliability.
Preferably in the aforementioned aspect, the insulating layer has a lower silicon oxide film and an upper silicon nitride film. The upper electrode is formed between the lower electrode and the side wall of the lower silicon oxide film, and the lower electrode is in contact with the side wall of the upper silicon nitride film.
The silicon nitride film is in close contact with the upper end of the lower electrode, whereby a portion of the lower electrode along the side wall of the opening can be prevented from falling in a manufacturing step.
A method of manufacturing a semiconductor device having a capacitor according to still another aspect of the present invention includes the following steps:
First, a conductive region is formed at the main surface of a semiconductor substrate. A silicon nitride film is formed on the main surface of the semiconductor substrate. A first silicon oxide film containing an impurity is formed on the first silicon oxide film. A second silicon oxide film substantially containing no impurities is formed on the first silicon oxide film. An opening is formed through the silicon nitride film and the first and second silicon oxide films. A lower electrode of a capacitor electrically connected with the conductive region is formed along the side wall and the bottom wall of the opening. Etching is performed with aqueous hydrofluoric acid. After this etching, a capacitor dielectric layer is formed to cover the lower electrode.
In the method of manufacturing a semiconductor device having a capacitor according to this aspect of the present invention, the second silicon oxide film formed on the first silicon oxide film substantially contains no impurities such as phosphorus and boron, dissimilarly to the first silicon oxide film. Therefore, the second silicon oxide is more hardly etched by aqueous hydrofluoric acid than the first silicon oxide film, and serves as an etching stopper. Thus, aqueous hydrofluoric acid can be employed for removing a natural oxide film from the surface of the lower electrode. In such etching with hydrofluoric acid, silicon is harder to etch as compared with etching with buffer hydrofluoric acid containing ammonium fluoride. Therefore, silicon crystal grains of the lower electrode can be prevented from separating from an underlayer of silicon and the lower electrode can be prevented from being shorted to another lower electrode, whereby the semiconductor device is improved in reliability.
Preferably in the aforementioned aspect, the lower electrode is subjected to surface roughening so that a plurality of crystal grains on the surface thereof are located at a space from each other. The grain size of the crystal grains on the surface of the lower electrode after formation of the capacitor dielectric layer is not more than the grain size of the crystal grains on the surface of the lower electrode immediately after the surface roughening, and larger than such a grain size that the crystal grains on the surface of the lower electrode separate from the lower electrode.
Thus, the crystal grains can be prevented from separating from the surface of the lower electrode, and the lower electrode can be prevented from being shorted to another lower electrode. In this specification, xe2x80x9csuch a grain size that the crystal grains on the surface of the lower electrode separate from the lower electrodexe2x80x9d is less than {fraction (1/1000)} of the grain size of the crystal grains on the surface of the lower electrode immediately after the surface roughening.
A method of manufacturing a semiconductor device having a capacitor according to a further aspect of the present invention includes the following steps:
First, a conductive region is formed at the main surface of a semiconductor substrate. Then, an insulating layer having an opening is formed on the main surface of the semiconductor substrate. A conductive layer is formed on the insulating layer to be electrically connected with the conductive region and to be along the side wall and the bottom wall of the opening. A mask layer is formed only in the opening. A lower electrode of a capacitor is formed from the conductive layer so that the upper end of a portion of the conductive layer along the side wall of the opening is located downward beyond the upper surface of the insulating layer by performing isotropic etching for removing a portion of the conductive layer exposed from the mask layer.
In the method of manufacturing a semiconductor device having a capacitor according to this aspect of the present invention, the lower electrode of the capacitor is so formed that the upper end thereof is located downward beyond the upper surface of the insulating layer. Thus, the lower electrode can be prevented from being shorted to another lower electrode by breakage of the upper end of the lower electrode projecting beyond the upper surface of the insulating layer, and the semiconductor device is improved in reliability.
A method of manufacturing a semiconductor device having a capacitor according to a further aspect of the present invention includes the following steps:
First, a conductive region is formed at the main surface of a semiconductor substrate. An insulating layer having an opening is formed on the main surface of the semiconductor substrate. A lower electrode of a capacitor electrically connected with the conductive region is formed along the side wall and the bottom wall of the opening. Etching is performed on the lower electrode with aqueous hydrofluoric acid containing phosphorus.
In the method of manufacturing a semiconductor device having a capacitor according to this aspect of the present invention, the aqueous hydrofluoric acid saturated with addition of phosphorus is so employed as to prevent reaction between water contained in the aqueous hydrofluoric acid and phosphorus contained in the lower electrode. Therefore, phosphorus is prevented from elution from the lower electrode and the conductivity of the capacitor can be kept excellent, whereby a large capacitance can be ensured and the semiconductor device is improved in reliability.
A method of manufacturing a semiconductor device having a capacitor according to a further aspect of the present invention includes the following steps:
First, a conductive region is formed at the main surface of a semiconductor substrate. An insulating layer having an opening is formed on the main surface of the semiconductor substrate. A lower electrode of a capacitor electrically connected with the conductive region, along the side wall and the bottom wall of the opening and having a surface formed of a plurality of crystal grains thereof is formed. Etching is performed for controlling the space between the plurality of crystal grain sizes of the surface of the lower electrode. A capacitor dielectric layer covering the lower electrode and having a thickness less than half the space between the crystal grains of the surface of the lower electrode is formed.
In the method of manufacturing a semiconductor device having a capacitor according to this aspect of the present invention, the capacitor dielectric layer, having the thickness less than half the space between the crystal grains on the surface of the lower electrode, is not completely embedded in clearances between the crystal grains. Therefore, an upper electrode can fill up the clearances between the crystal grains of the lower electrode to increase opposed areas of the lower electrode and the upper electrode, whereby a large capacitance can be ensured and the semiconductor device is improved in reliability.
Preferably in the aforementioned aspect, the lower electrode is formed to have a plurality of holes. A clearance is formed between the lower electrode and the side wall of the insulating layer by etching the side wall of the insulating layer through the plurality of holes. An upper electrode of the capacitor is formed to be opposed to the lower electrode with the capacitor dielectric layer in the clearance therebetween.
Thus, the lower electrode can be opposed to the upper electrode on both of the surface closer to the insulating layer and the opposite surface, whereby the capacitance can be increased and the semiconductor device is further improved in reliability.
Preferably in the aforementioned aspect, the step of forming the insulating layer includes steps of forming a silicon oxide film and forming a silicon nitride film on the silicon oxide film. The clearance is formed between the lower electrode and the side wall of the silicon oxide film.
This silicon nitride film is in close contact with the upper end of the lower electrode, whereby a portion of the lower electrode along the side wall of the opening can be prevented from falling during the manufacturing steps.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.